sieni
/
linux
mirror of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

dt-bindings: clock: qcom: Add Kaanapali Global clock controller 

Add device tree bindings for the global clock controller on Qualcomm
Kaanapali platform.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251030-gcc_kaanapali-v2-v2-3-a774a587af6f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Taniya Das 2025-10-30 16:39:06 +05:30 committed by Bjorn Andersson
parent 395e0e794f
commit 342d2a6074
2 changed files with 247 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
View File

@ -13,11 +13,15 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8750
See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
See also:
include/dt-bindings/clock/qcom,kaanapali-gcc.h
include/dt-bindings/clock/qcom,sm8750-gcc.h
properties:
compatible:
const: qcom,sm8750-gcc
enum:
- qcom,kaanapali-gcc
- qcom,sm8750-gcc
clocks:
items:

241
include/dt-bindings/clock/qcom,kaanapali-gcc.h Normal file
View File

@ -0,0 +1,241 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_KAANAPALI_H
#define _DT_BINDINGS_CLK_QCOM_GCC_KAANAPALI_H
/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 2
#define GCC_BOOT_ROM_AHB_CLK 3
#define GCC_CAM_BIST_MCLK_AHB_CLK 4
#define GCC_CAMERA_AHB_CLK 5
#define GCC_CAMERA_HF_AXI_CLK 6
#define GCC_CAMERA_SF_AXI_CLK 7
#define GCC_CAMERA_XO_CLK 8
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10
#define GCC_CNOC_PCIE_SF_AXI_CLK 11
#define GCC_DDRSS_PCIE_SF_QTB_CLK 12
#define GCC_QMIP_CAMERA_CMD_AHB_CLK 13
#define GCC_DISP_HF_AXI_CLK 14
#define GCC_DISP_SF_AXI_CLK 15
#define GCC_EVA_AHB_CLK 16
#define GCC_EVA_AXI0_CLK 17
#define GCC_EVA_AXI0C_CLK 18
#define GCC_EVA_XO_CLK 19
#define GCC_GP1_CLK 20
#define GCC_GP1_CLK_SRC 21
#define GCC_GP2_CLK 22
#define GCC_GP2_CLK_SRC 23
#define GCC_GP3_CLK 24
#define GCC_GP3_CLK_SRC 25
#define GCC_GPLL0 26
#define GCC_GPLL0_OUT_EVEN 27
#define GCC_GPLL1 28
#define GCC_GPLL4 29
#define GCC_GPLL7 30
#define GCC_GPLL9 31
#define GCC_GPU_CFG_AHB_CLK 32
#define GCC_GPU_GEMNOC_GFX_CLK 33
#define GCC_GPU_GPLL0_CLK_SRC 34
#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 36
#define GCC_QMIP_GPU_AHB_CLK 37
#define GCC_PCIE_0_AUX_CLK 38
#define GCC_PCIE_0_AUX_CLK_SRC 39
#define GCC_PCIE_0_CFG_AHB_CLK 40
#define GCC_PCIE_0_MSTR_AXI_CLK 41
#define GCC_PCIE_0_PHY_AUX_CLK 42
#define GCC_PCIE_0_PHY_AUX_CLK_SRC 43
#define GCC_PCIE_0_PHY_RCHNG_CLK 44
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 45
#define GCC_PCIE_0_PIPE_CLK 46
#define GCC_PCIE_0_PIPE_CLK_SRC 47
#define GCC_PCIE_0_SLV_AXI_CLK 48
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49
#define GCC_PCIE_RSCC_CFG_AHB_CLK 50
#define GCC_PCIE_RSCC_XO_CLK 51
#define GCC_PDM2_CLK 52
#define GCC_PDM2_CLK_SRC 53
#define GCC_PDM_AHB_CLK 54
#define GCC_PDM_XO4_CLK 55
#define GCC_QUPV3_I2C_CORE_CLK 56
#define GCC_QUPV3_I2C_S0_CLK 57
#define GCC_QUPV3_I2C_S0_CLK_SRC 58
#define GCC_QUPV3_I2C_S1_CLK 59
#define GCC_QUPV3_I2C_S1_CLK_SRC 60
#define GCC_QUPV3_I2C_S2_CLK 61
#define GCC_QUPV3_I2C_S2_CLK_SRC 62
#define GCC_QUPV3_I2C_S3_CLK 63
#define GCC_QUPV3_I2C_S3_CLK_SRC 64
#define GCC_QUPV3_I2C_S4_CLK 65
#define GCC_QUPV3_I2C_S4_CLK_SRC 66
#define GCC_QUPV3_I2C_S_AHB_CLK 67
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 68
#define GCC_QUPV3_WRAP1_CORE_CLK 69
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 70
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 71
#define GCC_QUPV3_WRAP1_S0_CLK 72
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73
#define GCC_QUPV3_WRAP1_S1_CLK 74
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75
#define GCC_QUPV3_WRAP1_S2_CLK 76
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77
#define GCC_QUPV3_WRAP1_S3_CLK 78
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79
#define GCC_QUPV3_WRAP1_S4_CLK 80
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81
#define GCC_QUPV3_WRAP1_S5_CLK 82
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83
#define GCC_QUPV3_WRAP1_S6_CLK 84
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 85
#define GCC_QUPV3_WRAP1_S7_CLK 86
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 87
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 88
#define GCC_QUPV3_WRAP2_CORE_CLK 89
#define GCC_QUPV3_WRAP2_S0_CLK 90
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 91
#define GCC_QUPV3_WRAP2_S1_CLK 92
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 93
#define GCC_QUPV3_WRAP2_S2_CLK 94
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 95
#define GCC_QUPV3_WRAP2_S3_CLK 96
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 97
#define GCC_QUPV3_WRAP2_S4_CLK 98
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 99
#define GCC_QUPV3_WRAP3_CORE_2X_CLK 100
#define GCC_QUPV3_WRAP3_CORE_CLK 101
#define GCC_QUPV3_WRAP3_IBI_CTRL_0_CLK_SRC 102
#define GCC_QUPV3_WRAP3_IBI_CTRL_1_CLK 103
#define GCC_QUPV3_WRAP3_IBI_CTRL_2_CLK 104
#define GCC_QUPV3_WRAP3_S0_CLK 105
#define GCC_QUPV3_WRAP3_S0_CLK_SRC 106
#define GCC_QUPV3_WRAP3_S1_CLK 107
#define GCC_QUPV3_WRAP3_S1_CLK_SRC 108
#define GCC_QUPV3_WRAP3_S2_CLK 109
#define GCC_QUPV3_WRAP3_S2_CLK_SRC 110
#define GCC_QUPV3_WRAP3_S3_CLK 111
#define GCC_QUPV3_WRAP3_S3_CLK_SRC 112
#define GCC_QUPV3_WRAP3_S4_CLK 113
#define GCC_QUPV3_WRAP3_S4_CLK_SRC 114
#define GCC_QUPV3_WRAP3_S5_CLK 115
#define GCC_QUPV3_WRAP3_S5_CLK_SRC 116
#define GCC_QUPV3_WRAP4_CORE_2X_CLK 117
#define GCC_QUPV3_WRAP4_CORE_CLK 118
#define GCC_QUPV3_WRAP4_S0_CLK 119
#define GCC_QUPV3_WRAP4_S0_CLK_SRC 120
#define GCC_QUPV3_WRAP4_S1_CLK 121
#define GCC_QUPV3_WRAP4_S1_CLK_SRC 122
#define GCC_QUPV3_WRAP4_S2_CLK 123
#define GCC_QUPV3_WRAP4_S2_CLK_SRC 124
#define GCC_QUPV3_WRAP4_S3_CLK 125
#define GCC_QUPV3_WRAP4_S3_CLK_SRC 126
#define GCC_QUPV3_WRAP4_S4_CLK 127
#define GCC_QUPV3_WRAP4_S4_CLK_SRC 128
#define GCC_QUPV3_WRAP_1_M_AXI_CLK 129
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 130
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 131
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 132
#define GCC_QUPV3_WRAP_3_IBI_1_AHB_CLK 133
#define GCC_QUPV3_WRAP_3_IBI_2_AHB_CLK 134
#define GCC_QUPV3_WRAP_3_M_AHB_CLK 135
#define GCC_QUPV3_WRAP_3_S_AHB_CLK 136
#define GCC_QUPV3_WRAP_4_M_AHB_CLK 137
#define GCC_QUPV3_WRAP_4_S_AHB_CLK 138
#define GCC_SDCC2_AHB_CLK 139
#define GCC_SDCC2_APPS_CLK 140
#define GCC_SDCC2_APPS_CLK_SRC 141
#define GCC_SDCC4_AHB_CLK 142
#define GCC_SDCC4_APPS_CLK 143
#define GCC_SDCC4_APPS_CLK_SRC 144
#define GCC_UFS_PHY_AHB_CLK 145
#define GCC_UFS_PHY_AXI_CLK 146
#define GCC_UFS_PHY_AXI_CLK_SRC 147
#define GCC_UFS_PHY_ICE_CORE_CLK 148
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 149
#define GCC_UFS_PHY_PHY_AUX_CLK 150
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 151
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 152
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 153
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 154
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 155
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 156
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 157
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 158
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 159
#define GCC_USB30_PRIM_MASTER_CLK 160
#define GCC_USB30_PRIM_MASTER_CLK_SRC 161
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 162
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 163
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 164
#define GCC_USB30_PRIM_SLEEP_CLK 165
#define GCC_USB3_PRIM_PHY_AUX_CLK 166
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 167
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 168
#define GCC_USB3_PRIM_PHY_PIPE_CLK 169
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 170
#define GCC_VIDEO_AHB_CLK 171
#define GCC_VIDEO_AXI0_CLK 172
#define GCC_VIDEO_AXI1_CLK 173
#define GCC_VIDEO_XO_CLK 174
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 175
#define GCC_QMIP_CAMERA_RT_AHB_CLK 176
#define GCC_QMIP_DISP_DCP_SF_AHB_CLK 177
#define GCC_QMIP_PCIE_AHB_CLK 178
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 179
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 180
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 181
#define GCC_DISP_AHB_CLK 182
/* GCC power domains */
#define GCC_PCIE_0_GDSC 0
#define GCC_PCIE_0_PHY_GDSC 1
#define GCC_UFS_MEM_PHY_GDSC 2
#define GCC_UFS_PHY_GDSC 3
#define GCC_USB30_PRIM_GDSC 4
#define GCC_USB3_PHY_GDSC 5
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_BCR 1
#define GCC_EVA_AXI0_CLK_ARES 2
#define GCC_EVA_AXI0C_CLK_ARES 3
#define GCC_EVA_BCR 4
#define GCC_GPU_BCR 5
#define GCC_PCIE_0_BCR 6
#define GCC_PCIE_0_LINK_DOWN_BCR 7
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 8
#define GCC_PCIE_0_PHY_BCR 9
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 10
#define GCC_PCIE_PHY_BCR 11
#define GCC_PCIE_PHY_CFG_AHB_BCR 12
#define GCC_PCIE_PHY_COM_BCR 13
#define GCC_PCIE_RSCC_BCR 14
#define GCC_PDM_BCR 15
#define GCC_QUPV3_WRAPPER_1_BCR 16
#define GCC_QUPV3_WRAPPER_2_BCR 17
#define GCC_QUPV3_WRAPPER_3_BCR 18
#define GCC_QUPV3_WRAPPER_4_BCR 19
#define GCC_QUPV3_WRAPPER_I2C_BCR 20
#define GCC_QUSB2PHY_PRIM_BCR 21
#define GCC_QUSB2PHY_SEC_BCR 22
#define GCC_SDCC2_BCR 23
#define GCC_SDCC4_BCR 24
#define GCC_UFS_PHY_BCR 25
#define GCC_USB30_PRIM_BCR 26
#define GCC_USB3_DP_PHY_PRIM_BCR 27
#define GCC_USB3_DP_PHY_SEC_BCR 28
#define GCC_USB3_PHY_PRIM_BCR 29
#define GCC_USB3_PHY_SEC_BCR 30
#define GCC_USB3PHY_PHY_PRIM_BCR 31
#define GCC_USB3PHY_PHY_SEC_BCR 32
#define GCC_VIDEO_AXI0_CLK_ARES 33
#define GCC_VIDEO_AXI1_CLK_ARES 34
#define GCC_VIDEO_BCR 35
#define GCC_VIDEO_XO_CLK_ARES 36
#endif