dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema
Convert the Marvell SoC core clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521210844.62613-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Rob Herring (Arm)
Stephen Boyd
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75cc48275f
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/marvell,mvebu-core-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell MVEBU SoC core clock
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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- Gregory Clement <gregory.clement@bootlin.com>
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description: >
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Marvell MVEBU SoCs usually allow to determine core clock frequencies by
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reading the Sample-At-Reset (SAR) register. The core clock consumer should
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specify the desired clock by having the clock ID in its "clocks" phandle cell.
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The following is a list of provided IDs and clock names on Armada 370/XP:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = nbclk (L2 Cache clock)
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3 = hclk (DRAM control clock)
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4 = dramclk (DDR clock)
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The following is a list of provided IDs and clock names on Armada 375:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = l2clk (L2 Cache clock)
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3 = ddrclk (DDR clock)
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The following is a list of provided IDs and clock names on Armada 380/385:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = l2clk (L2 Cache clock)
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3 = ddrclk (DDR clock)
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The following is a list of provided IDs and clock names on Armada 39x:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = nbclk (Coherent Fabric clock)
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3 = hclk (SDRAM Controller Internal Clock)
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4 = dclk (SDRAM Interface Clock)
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5 = refclk (Reference Clock)
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The following is a list of provided IDs and clock names on 98dx3236:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = ddrclk (DDR clock)
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3 = mpll (MPLL Clock)
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The following is a list of provided IDs and clock names on Kirkwood and Dove:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU0 clock)
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2 = l2clk (L2 Cache clock derived from CPU0 clock)
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3 = ddrclk (DDR controller clock derived from CPU0 clock)
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The following is a list of provided IDs and clock names on Orion5x:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU0 clock)
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2 = ddrclk (DDR controller clock derived from CPU0 clock)
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properties:
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compatible:
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enum:
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- marvell,armada-370-core-clock
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- marvell,armada-375-core-clock
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- marvell,armada-380-core-clock
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- marvell,armada-390-core-clock
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- marvell,armada-xp-core-clock
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- marvell,dove-core-clock
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- marvell,kirkwood-core-clock
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- marvell,mv88f5181-core-clock
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- marvell,mv88f5182-core-clock
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- marvell,mv88f5281-core-clock
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- marvell,mv88f6180-core-clock
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- marvell,mv88f6183-core-clock
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- marvell,mv98dx1135-core-clock
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- marvell,mv98dx3236-core-clock
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clock-output-names:
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description: Overwrite default clock output names.
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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@ -1,87 +0,0 @@
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* Core Clock bindings for Marvell MVEBU SoCs
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Marvell MVEBU SoCs usually allow to determine core clock frequencies by
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reading the Sample-At-Reset (SAR) register. The core clock consumer should
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specify the desired clock by having the clock ID in its "clocks" phandle cell.
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The following is a list of provided IDs and clock names on Armada 370/XP:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = nbclk (L2 Cache clock)
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3 = hclk (DRAM control clock)
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4 = dramclk (DDR clock)
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The following is a list of provided IDs and clock names on Armada 375:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = l2clk (L2 Cache clock)
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3 = ddrclk (DDR clock)
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The following is a list of provided IDs and clock names on Armada 380/385:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = l2clk (L2 Cache clock)
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3 = ddrclk (DDR clock)
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The following is a list of provided IDs and clock names on Armada 39x:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = nbclk (Coherent Fabric clock)
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3 = hclk (SDRAM Controller Internal Clock)
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4 = dclk (SDRAM Interface Clock)
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5 = refclk (Reference Clock)
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The following is a list of provided IDs and clock names on 98dx3236:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = ddrclk (DDR clock)
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3 = mpll (MPLL Clock)
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The following is a list of provided IDs and clock names on Kirkwood and Dove:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU0 clock)
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2 = l2clk (L2 Cache clock derived from CPU0 clock)
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3 = ddrclk (DDR controller clock derived from CPU0 clock)
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The following is a list of provided IDs and clock names on Orion5x:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU0 clock)
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2 = ddrclk (DDR controller clock derived from CPU0 clock)
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Required properties:
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- compatible : shall be one of the following:
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"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
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"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
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"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
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"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
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"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
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"marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
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"marvell,dove-core-clock" - for Dove SoC core clocks
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"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
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"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
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"marvell,mv98dx1135-core-clock" - for Kirkwood 98dx1135 SoC
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"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
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"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
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"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
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"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
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- reg : shall be the register address of the Sample-At-Reset (SAR) register
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- #clock-cells : from common clock binding; shall be set to 1
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Optional properties:
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- clock-output-names : from common clock binding; allows overwrite default clock
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output names ("tclk", "cpuclk", "l2clk", "ddrclk")
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Example:
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core_clk: core-clocks@d0214 {
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compatible = "marvell,dove-core-clock";
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reg = <0xd0214 0x4>;
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#clock-cells = <1>;
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};
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spi0: spi@10600 {
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compatible = "marvell,orion-spi";
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/* ... */
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/* get tclk from core clock provider */
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clocks = <&core_clk 0>;
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};
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