spi: rockchip-sfc: Support pm ops
Support system_sleep and runtime_pm ops. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://patch.msgid.link/20241208130311.1324024-1-jon.lin@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jon Lin
Mark Brown
parent
3f3b063e0c
commit
8011709906
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@ -13,12 +13,14 @@
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#include <linux/completion.h>
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#include <linux/dma-mapping.h>
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#include <linux/iopoll.h>
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#include <linux/interrupt.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/spi/spi-mem.h>
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/* System control */
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@ -150,11 +152,9 @@
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/* Data */
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#define SFC_DATA 0x108
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/* The controller and documentation reports that it supports up to 4 CS
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* devices (0-3), however I have only been able to test a single CS (CS 0)
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* due to the configuration of my device.
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*/
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#define SFC_MAX_CHIPSELECT_NUM 4
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#define SFC_CS1_REG_OFFSET 0x200
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#define SFC_MAX_CHIPSELECT_NUM 2
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/* The SFC can transfer max 16KB - 1 at one time
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* we set it to 15.5KB here for alignment.
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@ -169,12 +169,14 @@
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*/
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#define SFC_MAX_SPEED (150 * 1000 * 1000)
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#define ROCKCHIP_AUTOSUSPEND_DELAY 2000
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struct rockchip_sfc {
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struct device *dev;
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void __iomem *regbase;
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struct clk *hclk;
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struct clk *clk;
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u32 frequency;
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u32 speed[SFC_MAX_CHIPSELECT_NUM];
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/* virtual mapped addr for dma_buffer */
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void *buffer;
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dma_addr_t dma_buffer;
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@ -301,6 +303,7 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
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u32 len)
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{
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u32 ctrl = 0, cmd = 0;
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u8 cs = spi_get_chipselect(mem->spi, 0);
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/* set CMD */
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cmd = op->cmd.opcode;
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@ -314,7 +317,8 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
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cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
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} else {
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cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
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writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
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writel(op->addr.nbytes * 8 - 1,
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sfc->regbase + cs * SFC_CS1_REG_OFFSET + SFC_ABIT);
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}
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ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
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@ -346,7 +350,7 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
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/* set the Controller */
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ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
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cmd |= spi_get_chipselect(mem->spi, 0) << SFC_CMD_CS_SHIFT;
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cmd |= cs << SFC_CMD_CS_SHIFT;
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dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
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op->addr.nbytes, op->addr.buswidth,
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@ -354,7 +358,7 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
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dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n",
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ctrl, cmd, op->addr.val, len);
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writel(ctrl, sfc->regbase + SFC_CTRL);
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writel(ctrl, sfc->regbase + cs * SFC_CS1_REG_OFFSET + SFC_CTRL);
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writel(cmd, sfc->regbase + SFC_CMD);
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if (op->addr.nbytes)
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writel(op->addr.val, sfc->regbase + SFC_ADDR);
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@ -500,14 +504,22 @@ static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op
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struct rockchip_sfc *sfc = spi_controller_get_devdata(mem->spi->controller);
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u32 len = op->data.nbytes;
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int ret;
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u8 cs = spi_get_chipselect(mem->spi, 0);
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if (unlikely(mem->spi->max_speed_hz != sfc->frequency) && !has_acpi_companion(sfc->dev)) {
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ret = pm_runtime_get_sync(sfc->dev);
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if (ret < 0) {
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pm_runtime_put_noidle(sfc->dev);
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return ret;
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}
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if (unlikely(mem->spi->max_speed_hz != sfc->speed[cs]) &&
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!has_acpi_companion(sfc->dev)) {
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ret = clk_set_rate(sfc->clk, mem->spi->max_speed_hz);
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if (ret)
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return ret;
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sfc->frequency = mem->spi->max_speed_hz;
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goto out;
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sfc->speed[cs] = mem->spi->max_speed_hz;
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dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n",
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sfc->frequency, clk_get_rate(sfc->clk));
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sfc->speed[cs], clk_get_rate(sfc->clk));
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}
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rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
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@ -524,11 +536,17 @@ static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op
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if (ret != len) {
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dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir);
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return -EIO;
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ret = -EIO;
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goto out;
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}
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}
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return rockchip_sfc_xfer_done(sfc, 100000);
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ret = rockchip_sfc_xfer_done(sfc, 100000);
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out:
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pm_runtime_mark_last_busy(sfc->dev);
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pm_runtime_put_autosuspend(sfc->dev);
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return ret;
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}
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static int rockchip_sfc_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
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@ -570,6 +588,7 @@ static int rockchip_sfc_probe(struct platform_device *pdev)
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struct spi_controller *host;
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struct rockchip_sfc *sfc;
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int ret;
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u32 i, val;
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host = devm_spi_alloc_host(&pdev->dev, sizeof(*sfc));
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if (!host)
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@ -602,9 +621,12 @@ static int rockchip_sfc_probe(struct platform_device *pdev)
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"Failed to get sfc ahb clk\n");
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if (has_acpi_companion(&pdev->dev)) {
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ret = device_property_read_u32(&pdev->dev, "clock-frequency", &sfc->frequency);
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ret = device_property_read_u32(&pdev->dev, "clock-frequency", &val);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "Failed to find clock-frequency\n");
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return dev_err_probe(&pdev->dev, ret,
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"Failed to find clock-frequency in ACPI\n");
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for (i = 0; i < SFC_MAX_CHIPSELECT_NUM; i++)
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sfc->speed[i] = val;
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}
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sfc->use_dma = !of_property_read_bool(sfc->dev->of_node, "rockchip,sfc-no-dma");
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@ -646,6 +668,8 @@ static int rockchip_sfc_probe(struct platform_device *pdev)
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goto err_irq;
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}
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platform_set_drvdata(pdev, sfc);
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ret = rockchip_sfc_init(sfc);
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if (ret)
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goto err_irq;
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@ -653,12 +677,27 @@ static int rockchip_sfc_probe(struct platform_device *pdev)
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sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
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sfc->version = rockchip_sfc_get_version(sfc);
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ret = spi_register_controller(host);
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pm_runtime_set_autosuspend_delay(dev, ROCKCHIP_AUTOSUSPEND_DELAY);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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pm_runtime_get_noresume(dev);
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ret = devm_spi_register_controller(dev, host);
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if (ret)
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goto err_irq;
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goto err_pm_runtime_free;
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return 0;
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err_pm_runtime_free:
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pm_runtime_get_sync(dev);
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pm_runtime_put_noidle(dev);
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pm_runtime_disable(dev);
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pm_runtime_set_suspended(dev);
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pm_runtime_dont_use_autosuspend(dev);
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err_irq:
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clk_disable_unprepare(sfc->clk);
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err_clk:
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@ -678,6 +717,74 @@ static void rockchip_sfc_remove(struct platform_device *pdev)
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clk_disable_unprepare(sfc->hclk);
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}
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#ifdef CONFIG_PM
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static int rockchip_sfc_runtime_suspend(struct device *dev)
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{
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struct rockchip_sfc *sfc = dev_get_drvdata(dev);
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clk_disable_unprepare(sfc->clk);
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clk_disable_unprepare(sfc->hclk);
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return 0;
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}
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static int rockchip_sfc_runtime_resume(struct device *dev)
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{
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struct rockchip_sfc *sfc = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(sfc->hclk);
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if (ret < 0)
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return ret;
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ret = clk_prepare_enable(sfc->clk);
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if (ret < 0)
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clk_disable_unprepare(sfc->hclk);
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return ret;
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}
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#endif /* CONFIG_PM */
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#ifdef CONFIG_PM_SLEEP
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static int rockchip_sfc_suspend(struct device *dev)
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{
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pinctrl_pm_select_sleep_state(dev);
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return pm_runtime_force_suspend(dev);
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}
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static int rockchip_sfc_resume(struct device *dev)
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{
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struct rockchip_sfc *sfc = dev_get_drvdata(dev);
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int ret;
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ret = pm_runtime_force_resume(dev);
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if (ret < 0)
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return ret;
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pinctrl_pm_select_default_state(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
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pm_runtime_put_noidle(dev);
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return ret;
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}
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rockchip_sfc_init(sfc);
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return 0;
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}
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#endif /* CONFIG_PM_SLEEP */
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static const struct dev_pm_ops rockchip_sfc_pm_ops = {
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SET_RUNTIME_PM_OPS(rockchip_sfc_runtime_suspend,
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rockchip_sfc_runtime_resume, NULL)
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SET_SYSTEM_SLEEP_PM_OPS(rockchip_sfc_suspend, rockchip_sfc_resume)
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};
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static const struct of_device_id rockchip_sfc_dt_ids[] = {
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{ .compatible = "rockchip,sfc"},
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{ /* sentinel */ }
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@ -688,6 +795,7 @@ static struct platform_driver rockchip_sfc_driver = {
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.driver = {
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.name = "rockchip-sfc",
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.of_match_table = rockchip_sfc_dt_ids,
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.pm = &rockchip_sfc_pm_ops,
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},
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.probe = rockchip_sfc_probe,
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.remove = rockchip_sfc_remove,
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