Microchip AT91 SoC updates for v6.15
This update includes: - SoC driver support for Microchip SAMA7D65 - power management support for Microchip SAMA7D65 - power management fixes - documentation fixes -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCZ8/y2AAKCRCejrg/N2X7 /Tm9AQDy++uuWZnWDALQrp7fDNZE80nkAtPkdhW14OWMB/cr7AEAoL4xDkvXkoUx YxVMi2sPaZYmBkbOYBhFYOXIZC7SpgI= =FliT -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmfbOEoACgkQYKtH/8kJ UifvQA/7Bq9sAYwFcHYm7tQ13oF9hXXcMsC65jlE+BzzyjvpwgVjYLjYsAAJintv v4Wuu6/J84fplBuUa+pYy6QTFUm1VfL7j2YQjdUUX6OiF/q3livYxjySKwUrfDsD njy1pIJy783sUvsZiPHgvc9zwEIuYy0oDaWW2AVhfYSialbBI8jVcQ9A4HQNxqZh b2Xdb+ewS37PiWL95KejJ1cbJ+KXaW4EZAsgI/mTXsiDSxBsILl/kmrf+jqkkyE1 vqGqufTKEVxVxsw3yptEHNOQArg1PfK+LsAuXaBgLb2ybar7PunVVuW77UxxIV6Z rRIpGS7fCtwE7CAaT1x+o+tbuiH2Xvp/nDXndmjcyn4axR4XIe8y3Af0a1dFN7yP JN4ZdyGZJYuGDrQgS3nV2hDU5/NDahaOB7lxZpXSWfoarTQD8C/AiiAIPVpEHTrf xi++NU7k8dtXyxwydSqxyGSD+ZRFkov7BkeShGx9RNL0QHF6EvxJyCWkOu1UNR6y HPl0kzlwa513DR+ouJDUT8NFDOyDW2XH80edINinmCaAq1Y5RLfjvzf/yRIZETWm CoGLb6JjRojSfQrNaTN4qg4sIT+ZGYEkB1xU6NJpkUbKumpBgsdswGST79mPPsLg lekPs3qRar3VDX5w0Sm7C2/X9FrlHsmLUZBYICNO42ue1JzKQ4E= =qC90 -----END PGP SIGNATURE----- Merge tag 'at91-soc-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/arm Microchip AT91 SoC updates for v6.15 This update includes: - SoC driver support for Microchip SAMA7D65 - power management support for Microchip SAMA7D65 - power management fixes - documentation fixes * tag 'at91-soc-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: pm: Enable ULP0/ULP1 for SAMA7D65 ARM: at91: pm: Add Backup mode for SAMA7D65 ARM: at91: pm: add DT compatible support for sama7d65 ARM: at91: pm: fix at91_suspend_finish for ZQ calibration dt-bindings: ARM: at91: add Calao USB boards dt-bindings: ARM: at91: make separate entry for Olimex board ARM: at91: Add Support in SoC driver for SAMA7D65 dt-bindings: atmel-sysreg: Add SAMA7D65 Chip ID Link: https://lore.kernel.org/r/20250312173755.975074-2-claudiu.beznea@tuxon.dev Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
911a44cf6d
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@ -22,8 +22,6 @@ properties:
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- items:
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- const: atmel,at91rm9200
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- items:
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- enum:
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- olimex,sam9-l9260
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- enum:
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- atmel,at91sam9260
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- atmel,at91sam9261
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@ -36,6 +34,37 @@ properties:
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- atmel,at91sam9x60
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- const: atmel,at91sam9
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- description: Olimex SAM9-L9260
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items:
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- const: olimex,sam9-l9260
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- const: atmel,at91sam9260
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- const: atmel,at91sam9
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- description: Calao USB A9260
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items:
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- const: calao,usb-a9260
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- const: atmel,at91sam9260
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- const: atmel,at91sam9
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- description: Calao USB A9263
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items:
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- const: calao,usb-a9263
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- const: atmel,at91sam9263
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- const: atmel,at91sam9
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- description: Calao USB A9G20
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items:
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- const: calao,usb-a9g20
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- const: atmel,at91sam9g20
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- const: atmel,at91sam9
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- description: Calao USB A9G20-LPW
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items:
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- const: calao,usb-a9g20-lpw
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- const: calao,usb-a9g20
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- const: atmel,at91sam9g20
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- const: atmel,at91sam9
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- items:
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- enum:
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- overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board
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@ -2,6 +2,7 @@ Atmel system registers
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Chipid required properties:
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- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
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"microchip,sama7d65-chipid"
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- reg : Should contain registers location and length
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PIT Timer required properties:
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@ -222,13 +222,16 @@ static const struct of_device_id sam9x60_ws_ids[] = {
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{ /* sentinel */ }
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};
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static const struct of_device_id sama7g5_ws_ids[] = {
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static const struct of_device_id sama7_ws_ids[] = {
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{ .compatible = "microchip,sama7d65-rtc", .data = &ws_info[1] },
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{ .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
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{ .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
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{ .compatible = "usb-ohci", .data = &ws_info[2] },
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{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
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{ .compatible = "usb-ehci", .data = &ws_info[2] },
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{ .compatible = "microchip,sama7d65-sdhci", .data = &ws_info[3] },
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{ .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
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{ .compatible = "microchip,sama7d65-rtt", .data = &ws_info[4] },
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{ .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
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{ /* sentinel */ }
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};
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@ -545,11 +548,12 @@ extern u32 at91_pm_suspend_in_sram_sz;
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static int at91_suspend_finish(unsigned long val)
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{
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unsigned char modified_gray_code[] = {
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0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
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0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
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0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
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0x10, 0x11,
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/* SYNOPSYS workaround to fix a bug in the calibration logic */
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unsigned char modified_fix_code[] = {
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0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18,
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0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13,
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0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14,
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0x1e, 0x1f,
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};
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unsigned int tmp, index;
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int i;
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@ -560,25 +564,25 @@ static int at91_suspend_finish(unsigned long val)
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* restore the ZQ0SR0 with the value saved here. But the
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* calibration is buggy and restoring some values from ZQ0SR0
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* is forbidden and risky thus we need to provide processed
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* values for these (modified gray code values).
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* values for these.
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*/
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tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
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/* Store pull-down output impedance select. */
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index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
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soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
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soc_pm.bu->ddr_phy_calibration[0] = modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDO_OFF;
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/* Store pull-up output impedance select. */
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index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
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soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
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soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PUO_OFF;
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/* Store pull-down on-die termination impedance select. */
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index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
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soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
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soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDODT_OFF;
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/* Store pull-up on-die termination impedance select. */
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index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
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soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
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soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SRO_PUODT_OFF;
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/*
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* The 1st 8 words of memory might get corrupted in the process
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@ -643,6 +647,11 @@ static void at91_pm_suspend(suspend_state_t state)
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at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
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&at91_pm_suspend_in_sram,
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at91_pm_suspend_in_sram_sz);
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if (IS_ENABLED(CONFIG_SOC_SAMA7D65)) {
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/* SHDWC.SR */
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readl(soc_pm.data.shdwc + 0x08);
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}
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} else {
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at91_suspend_finish(0);
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}
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@ -1061,7 +1070,8 @@ static int __init at91_pm_backup_init(void)
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int ret = -ENODEV, located = 0;
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if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
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!IS_ENABLED(CONFIG_SOC_SAMA7G5))
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!IS_ENABLED(CONFIG_SOC_SAMA7G5) &&
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!IS_ENABLED(CONFIG_SOC_SAMA7D65))
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return -EPERM;
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if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
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@ -1329,6 +1339,7 @@ struct pmc_info {
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unsigned long uhp_udp_mask;
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unsigned long mckr;
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unsigned long version;
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unsigned long mcks;
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};
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static const struct pmc_info pmc_infos[] __initconst = {
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@ -1360,8 +1371,14 @@ static const struct pmc_info pmc_infos[] __initconst = {
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{
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.mckr = 0x28,
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.version = AT91_PMC_V2,
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.mcks = 4,
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},
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{
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.uhp_udp_mask = AT91SAM926x_PMC_UHP,
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.mckr = 0x28,
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.version = AT91_PMC_V2,
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.mcks = 9,
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},
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};
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static const struct of_device_id atmel_pmc_ids[] __initconst = {
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@ -1378,6 +1395,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
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{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
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{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
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{ .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
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{ .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
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{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
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{ /* sentinel */ },
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};
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@ -1448,6 +1466,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
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soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
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soc_pm.data.pmc_mckr_offset = pmc->mckr;
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soc_pm.data.pmc_version = pmc->version;
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soc_pm.data.pmc_mcks = pmc->mcks;
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if (pm_idle)
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arm_pm_idle = pm_idle;
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@ -1671,7 +1690,7 @@ void __init sama7_pm_init(void)
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at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
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at91_pm_init(NULL);
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soc_pm.ws_ids = sama7g5_ws_ids;
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soc_pm.ws_ids = sama7_ws_ids;
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soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
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soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
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@ -39,6 +39,7 @@ struct at91_pm_data {
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unsigned int suspend_mode;
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unsigned int pmc_mckr_offset;
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unsigned int pmc_version;
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unsigned int pmc_mcks;
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};
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#endif
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@ -18,6 +18,8 @@ int main(void)
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pmc_mckr_offset));
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DEFINE(PM_DATA_PMC_VERSION, offsetof(struct at91_pm_data,
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pmc_version));
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DEFINE(PM_DATA_PMC_MCKS, offsetof(struct at91_pm_data,
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pmc_mcks));
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return 0;
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}
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@ -814,18 +814,20 @@ sr_dis_exit:
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.endm
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/**
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* at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock
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* at91_mckx_ps_enable: save MCK settings and switch it to main clock
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*
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* Side effects: overwrites tmp1, tmp2
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* Side effects: overwrites tmp1, tmp2, tmp3
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*/
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.macro at91_mckx_ps_enable
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#ifdef CONFIG_SOC_SAMA7
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ldr pmc, .pmc_base
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ldr tmp3, .mcks
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/* There are 4 MCKs we need to handle: MCK1..4 */
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/* Start at MCK1 and go until MCKs */
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mov tmp1, #1
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e_loop: cmp tmp1, #5
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beq e_done
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e_loop:
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cmp tmp1, tmp3
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bgt e_done
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/* Write MCK ID to retrieve the settings. */
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str tmp1, [pmc, #AT91_PMC_MCR_V2]
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@ -850,7 +852,37 @@ e_save_mck3:
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b e_ps
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e_save_mck4:
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cmp tmp1, #4
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bne e_save_mck5
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str tmp2, .saved_mck4
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b e_ps
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e_save_mck5:
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cmp tmp1, #5
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bne e_save_mck6
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str tmp2, .saved_mck5
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b e_ps
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e_save_mck6:
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cmp tmp1, #6
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bne e_save_mck7
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str tmp2, .saved_mck6
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b e_ps
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e_save_mck7:
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cmp tmp1, #7
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bne e_save_mck8
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str tmp2, .saved_mck7
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b e_ps
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e_save_mck8:
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cmp tmp1, #8
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bne e_save_mck9
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str tmp2, .saved_mck8
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b e_ps
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e_save_mck9:
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str tmp2, .saved_mck9
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e_ps:
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/* Use CSS=MAINCK and DIV=1. */
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@ -870,18 +902,20 @@ e_done:
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.endm
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/**
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* at91_mckx_ps_restore: restore MCK1..4 settings
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* at91_mckx_ps_restore: restore MCKx settings
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*
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* Side effects: overwrites tmp1, tmp2
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*/
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.macro at91_mckx_ps_restore
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#ifdef CONFIG_SOC_SAMA7
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ldr pmc, .pmc_base
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ldr tmp2, .mcks
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/* There are 4 MCKs we need to handle: MCK1..4 */
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/* Start from MCK1 and go up to MCKs */
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mov tmp1, #1
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r_loop: cmp tmp1, #5
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beq r_done
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r_loop:
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cmp tmp1, tmp2
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bgt r_done
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r_save_mck1:
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cmp tmp1, #1
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@ -902,7 +936,37 @@ r_save_mck3:
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b r_ps
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r_save_mck4:
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cmp tmp1, #4
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bne r_save_mck5
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ldr tmp2, .saved_mck4
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b r_ps
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r_save_mck5:
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cmp tmp1, #5
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bne r_save_mck6
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ldr tmp2, .saved_mck5
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b r_ps
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||||
|
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r_save_mck6:
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cmp tmp1, #6
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bne r_save_mck7
|
||||
ldr tmp2, .saved_mck6
|
||||
b r_ps
|
||||
|
||||
r_save_mck7:
|
||||
cmp tmp1, #7
|
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bne r_save_mck8
|
||||
ldr tmp2, .saved_mck7
|
||||
b r_ps
|
||||
|
||||
r_save_mck8:
|
||||
cmp tmp1, #8
|
||||
bne r_save_mck9
|
||||
ldr tmp2, .saved_mck8
|
||||
b r_ps
|
||||
|
||||
r_save_mck9:
|
||||
ldr tmp2, .saved_mck9
|
||||
|
||||
r_ps:
|
||||
/* Write MCK ID to retrieve the settings. */
|
||||
|
|
@ -921,6 +985,7 @@ r_ps:
|
|||
wait_mckrdy tmp1
|
||||
|
||||
add tmp1, tmp1, #1
|
||||
ldr tmp2, .mcks
|
||||
b r_loop
|
||||
r_done:
|
||||
#endif
|
||||
|
|
@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram)
|
|||
str tmp1, .memtype
|
||||
ldr tmp1, [r0, #PM_DATA_MODE]
|
||||
str tmp1, .pm_mode
|
||||
#ifdef CONFIG_SOC_SAMA7
|
||||
ldr tmp1, [r0, #PM_DATA_PMC_MCKS]
|
||||
str tmp1, .mcks
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ldrne below are here to preload their address in the TLB as access
|
||||
|
|
@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram)
|
|||
.word 0
|
||||
.pmc_version:
|
||||
.word 0
|
||||
#ifdef CONFIG_SOC_SAMA7
|
||||
.mcks:
|
||||
.word 0
|
||||
#endif
|
||||
.saved_mckr:
|
||||
.word 0
|
||||
.saved_pllar:
|
||||
|
|
@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram)
|
|||
.word 0
|
||||
.saved_mck4:
|
||||
.word 0
|
||||
.saved_mck5:
|
||||
.word 0
|
||||
.saved_mck6:
|
||||
.word 0
|
||||
.saved_mck7:
|
||||
.word 0
|
||||
.saved_mck8:
|
||||
.word 0
|
||||
.saved_mck9:
|
||||
.word 0
|
||||
#endif
|
||||
|
||||
ENTRY(at91_pm_suspend_in_sram_sz)
|
||||
|
|
|
|||
|
|
@ -246,6 +246,9 @@ static const struct at91_soc socs[] __initconst = {
|
|||
"samv70q19", "samv7"),
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_SAMA7
|
||||
AT91_SOC(SAMA7D65_CIDR_MATCH, AT91_CIDR_MASK_SAMA7G5,
|
||||
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7D65_EXID_MATCH,
|
||||
"sama7d65", "sama7d6"),
|
||||
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
|
||||
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH,
|
||||
"sama7g51", "sama7g5"),
|
||||
|
|
@ -305,6 +308,7 @@ static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
|
|||
void __iomem *regs;
|
||||
static const struct of_device_id chipids[] = {
|
||||
{ .compatible = "atmel,sama5d2-chipid" },
|
||||
{ .compatible = "microchip,sama7d65-chipid" },
|
||||
{ .compatible = "microchip,sama7g5-chipid" },
|
||||
{ },
|
||||
};
|
||||
|
|
@ -393,6 +397,7 @@ static const struct of_device_id at91_soc_allowed_list[] __initconst = {
|
|||
{ .compatible = "atmel,at91sam9", },
|
||||
{ .compatible = "atmel,sama5", },
|
||||
{ .compatible = "atmel,samv7", },
|
||||
{ .compatible = "microchip,sama7d65", },
|
||||
{ .compatible = "microchip,sama7g5", },
|
||||
{ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@ at91_soc_init(const struct at91_soc *socs);
|
|||
#define AT91SAM9N12_CIDR_MATCH 0x019a07a0
|
||||
#define SAM9X60_CIDR_MATCH 0x019b35a0
|
||||
#define SAM9X7_CIDR_MATCH 0x09750020
|
||||
#define SAMA7D65_CIDR_MATCH 0x00262100
|
||||
#define SAMA7G5_CIDR_MATCH 0x00162100
|
||||
|
||||
#define AT91SAM9M11_EXID_MATCH 0x00000001
|
||||
|
|
@ -75,6 +76,8 @@ at91_soc_init(const struct at91_soc *socs);
|
|||
#define SAM9X75_D5M_EXID_MATCH 0x00000010
|
||||
#define SAM9X75_EXID_MATCH 0x00000000
|
||||
|
||||
#define SAMA7D65_EXID_MATCH 0x00000080
|
||||
|
||||
#define SAMA7G51_EXID_MATCH 0x3
|
||||
#define SAMA7G52_EXID_MATCH 0x2
|
||||
#define SAMA7G53_EXID_MATCH 0x1
|
||||
|
|
|
|||
Loading…
Reference in New Issue