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MMC host: 

- sdhci: Fix timing selection for 1-bit bus width
  - sdhci-pci-gli: Fix DMA write corruption for GL9750
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Merge tag 'mmc-v7.0-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC fixes from Ulf Hansson:

 - sdhci: Fix timing selection for 1-bit bus width

 - sdhci-pci-gli: Fix DMA write corruption for GL9750

* tag 'mmc-v7.0-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
  mmc: sdhci: fix timing selection for 1-bit bus width
  mmc: sdhci-pci-gli: fix GL9750 DMA write corruption
This commit is contained in:
Linus Torvalds 2026-03-20 09:40:25 -07:00
parent f374ff79f4 5e3486e640
commit d07252736a
2 changed files with 17 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/mmc/host/sdhci-pci-gli.c
View File

@ -68,6 +68,9 @@
#define GLI_9750_MISC_TX1_DLY_VALUE 0x5
#define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26)
#define SDHCI_GLI_9750_GM_BURST_SIZE 0x510
#define SDHCI_GLI_9750_GM_BURST_SIZE_R_OSRC_LMT GENMASK(17, 16)
#define SDHCI_GLI_9750_TUNING_CONTROL 0x540
#define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)
#define GLI_9750_TUNING_CONTROL_EN_ON 0x1
@ -345,10 +348,16 @@ static void gli_set_9750(struct sdhci_host *host)
u32 misc_value;
u32 parameter_value;
u32 control_value;
u32 burst_value;
u16 ctrl2;
gl9750_wt_on(host);
/* clear R_OSRC_Lmt to avoid DMA write corruption */
burst_value = sdhci_readl(host, SDHCI_GLI_9750_GM_BURST_SIZE);
burst_value &= ~SDHCI_GLI_9750_GM_BURST_SIZE_R_OSRC_LMT;
sdhci_writel(host, burst_value, SDHCI_GLI_9750_GM_BURST_SIZE);
driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);

9
drivers/mmc/host/sdhci.c
View File

@ -4532,8 +4532,15 @@ int sdhci_setup_host(struct sdhci_host *host)
* their platform code before calling sdhci_add_host(), and we
* won't assume 8-bit width for hosts without that CAP.
*/
if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
if (host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA) {
host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400)
host->caps1 &= ~SDHCI_SUPPORT_HS400;
mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
mmc->caps &= ~(MMC_CAP_DDR | MMC_CAP_UHS);
} else {
mmc->caps |= MMC_CAP_4_BIT_DATA;
}
if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
mmc->caps &= ~MMC_CAP_CMD23;