net: dsa: yt921x: Add DCB/QoS support
Set up global DSCP/PCP priority mappings and add related DCB methods. Signed-off-by: David Yang <mmyangfl@gmail.com> Link: https://patch.msgid.link/20260131021854.3405036-6-mmyangfl@gmail.com Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
David Yang
Paolo Abeni
parent
95e6bcab3c
commit
d5f778353f
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@ -158,6 +158,7 @@ config NET_DSA_VITESSE_VSC73XX_PLATFORM
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config NET_DSA_YT921X
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tristate "Motorcomm YT9215 ethernet switch chip support"
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select NET_DSA_TAG_YT921X
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select NET_IEEE8021Q_HELPERS if DCB
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help
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This enables support for the Motorcomm YT9215 ethernet switch
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chip.
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@ -8,6 +8,7 @@
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* Copyright (c) 2025 David Yang
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*/
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#include <linux/dcbnl.h>
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#include <linux/etherdevice.h>
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#include <linux/if_bridge.h>
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#include <linux/if_hsr.h>
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@ -18,8 +19,11 @@
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#include <linux/of.h>
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#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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#include <linux/sort.h>
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#include <net/dsa.h>
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#include <net/dscp.h>
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#include <net/ieee8021q.h>
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#include "yt921x.h"
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@ -1774,8 +1778,11 @@ yt921x_vlan_aware_set(struct yt921x_priv *priv, int port, bool vlan_aware)
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{
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u32 ctrl;
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/* Abuse SVLAN for PCP parsing without polluting the FDB - it just works
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* despite YT921X_VLAN_CTRL_SVLAN_EN never being set
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*/
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if (!vlan_aware)
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ctrl = 0;
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ctrl = YT921X_PORT_IGR_TPIDn_STAG(0);
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else
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ctrl = YT921X_PORT_IGR_TPIDn_CTAG(0);
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return yt921x_reg_write(priv, YT921X_PORTn_IGR_TPID(port), ctrl);
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@ -2396,6 +2403,122 @@ yt921x_dsa_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
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port, res);
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}
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static int __maybe_unused
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yt921x_dsa_port_get_default_prio(struct dsa_switch *ds, int port)
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{
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struct yt921x_priv *priv = to_yt921x_priv(ds);
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u32 val;
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int res;
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mutex_lock(&priv->reg_lock);
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res = yt921x_reg_read(priv, YT921X_PORTn_QOS(port), &val);
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mutex_unlock(&priv->reg_lock);
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if (res)
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return res;
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return FIELD_GET(YT921X_PORT_QOS_PRIO_M, val);
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}
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static int __maybe_unused
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yt921x_dsa_port_set_default_prio(struct dsa_switch *ds, int port, u8 prio)
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{
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struct yt921x_priv *priv = to_yt921x_priv(ds);
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u32 mask;
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u32 ctrl;
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int res;
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if (prio >= YT921X_PRIO_NUM)
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return -EINVAL;
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mutex_lock(&priv->reg_lock);
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mask = YT921X_PORT_QOS_PRIO_M | YT921X_PORT_QOS_PRIO_EN;
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ctrl = YT921X_PORT_QOS_PRIO(prio) | YT921X_PORT_QOS_PRIO_EN;
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res = yt921x_reg_update_bits(priv, YT921X_PORTn_QOS(port), mask, ctrl);
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mutex_unlock(&priv->reg_lock);
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return res;
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}
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static int __maybe_unused appprios_cmp(const void *a, const void *b)
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{
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return ((const u8 *)b)[1] - ((const u8 *)a)[1];
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}
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static int __maybe_unused
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yt921x_dsa_port_get_apptrust(struct dsa_switch *ds, int port, u8 *sel,
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int *nselp)
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{
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struct yt921x_priv *priv = to_yt921x_priv(ds);
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u8 appprios[2][2] = {};
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int nsel;
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u32 val;
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int res;
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mutex_lock(&priv->reg_lock);
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res = yt921x_reg_read(priv, YT921X_PORTn_PRIO_ORD(port), &val);
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mutex_unlock(&priv->reg_lock);
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if (res)
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return res;
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appprios[0][0] = IEEE_8021QAZ_APP_SEL_DSCP;
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appprios[0][1] = (val >> (3 * YT921X_APP_SEL_DSCP)) & 7;
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appprios[1][0] = DCB_APP_SEL_PCP;
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appprios[1][1] = (val >> (3 * YT921X_APP_SEL_CVLAN_PCP)) & 7;
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sort(appprios, ARRAY_SIZE(appprios), sizeof(appprios[0]), appprios_cmp,
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NULL);
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nsel = 0;
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for (int i = 0; i < ARRAY_SIZE(appprios) && appprios[i][1]; i++) {
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sel[nsel] = appprios[i][0];
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nsel++;
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}
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*nselp = nsel;
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return 0;
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}
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static int __maybe_unused
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yt921x_dsa_port_set_apptrust(struct dsa_switch *ds, int port, const u8 *sel,
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int nsel)
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{
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struct yt921x_priv *priv = to_yt921x_priv(ds);
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struct device *dev = to_device(priv);
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u32 ctrl;
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int res;
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if (nsel > YT921X_APP_SEL_NUM)
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return -EINVAL;
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ctrl = 0;
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for (int i = 0; i < nsel; i++) {
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switch (sel[i]) {
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case IEEE_8021QAZ_APP_SEL_DSCP:
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ctrl |= YT921X_PORT_PRIO_ORD_APPm(YT921X_APP_SEL_DSCP,
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7 - i);
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break;
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case DCB_APP_SEL_PCP:
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ctrl |= YT921X_PORT_PRIO_ORD_APPm(YT921X_APP_SEL_CVLAN_PCP,
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7 - i);
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ctrl |= YT921X_PORT_PRIO_ORD_APPm(YT921X_APP_SEL_SVLAN_PCP,
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7 - i);
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break;
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default:
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dev_err(dev,
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"Invalid apptrust selector (at %d-th). Supported: dscp, pcp\n",
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i + 1);
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return -EOPNOTSUPP;
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}
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}
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mutex_lock(&priv->reg_lock);
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res = yt921x_reg_write(priv, YT921X_PORTn_PRIO_ORD(port), ctrl);
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mutex_unlock(&priv->reg_lock);
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return res;
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}
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static int yt921x_port_down(struct yt921x_priv *priv, int port)
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{
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u32 mask;
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@ -2720,6 +2843,13 @@ static int yt921x_port_setup(struct yt921x_priv *priv, int port)
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if (res)
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return res;
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/* Clear prio order (even if DCB is not enabled) to avoid unsolicited
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* priorities
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*/
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res = yt921x_reg_write(priv, YT921X_PORTn_PRIO_ORD(port), 0);
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if (res)
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return res;
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if (dsa_is_cpu_port(ds, port)) {
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/* Egress of CPU port is supposed to be completely controlled
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* via tagging, so set to oneway isolated (drop all packets
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@ -2763,6 +2893,66 @@ static int yt921x_dsa_port_setup(struct dsa_switch *ds, int port)
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return res;
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}
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/* Not "port" - DSCP mapping is global */
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static int __maybe_unused
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yt921x_dsa_port_get_dscp_prio(struct dsa_switch *ds, int port, u8 dscp)
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{
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struct yt921x_priv *priv = to_yt921x_priv(ds);
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u32 val;
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int res;
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mutex_lock(&priv->reg_lock);
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res = yt921x_reg_read(priv, YT921X_IPM_DSCPn(dscp), &val);
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mutex_unlock(&priv->reg_lock);
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if (res)
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return res;
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return FIELD_GET(YT921X_IPM_PRIO_M, val);
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}
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static int __maybe_unused
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yt921x_dsa_port_del_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, u8 prio)
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{
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struct yt921x_priv *priv = to_yt921x_priv(ds);
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u32 val;
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int res;
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mutex_lock(&priv->reg_lock);
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/* During a "dcb app replace" command, the new app table entry will be
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* added first, then the old one will be deleted. But the hardware only
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* supports one QoS class per DSCP value (duh), so if we blindly delete
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* the app table entry for this DSCP value, we end up deleting the
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* entry with the new priority. Avoid that by checking whether user
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* space wants to delete the priority which is currently configured, or
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* something else which is no longer current.
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*/
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res = yt921x_reg_read(priv, YT921X_IPM_DSCPn(dscp), &val);
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if (!res && FIELD_GET(YT921X_IPM_PRIO_M, val) == prio)
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res = yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp),
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YT921X_IPM_PRIO(IEEE8021Q_TT_BK));
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mutex_unlock(&priv->reg_lock);
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return res;
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}
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static int __maybe_unused
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yt921x_dsa_port_add_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, u8 prio)
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{
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struct yt921x_priv *priv = to_yt921x_priv(ds);
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int res;
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if (prio >= YT921X_PRIO_NUM)
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return -EINVAL;
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mutex_lock(&priv->reg_lock);
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res = yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp),
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YT921X_IPM_PRIO(prio));
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mutex_unlock(&priv->reg_lock);
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return res;
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}
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static int yt921x_edata_wait(struct yt921x_priv *priv, u32 *valp)
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{
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u32 val = YT921X_EDATA_DATA_IDLE;
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@ -2975,6 +3165,47 @@ static int yt921x_chip_setup_dsa(struct yt921x_priv *priv)
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return 0;
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}
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static int __maybe_unused yt921x_chip_setup_qos(struct yt921x_priv *priv)
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{
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u32 ctrl;
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int res;
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/* DSCP to internal priorities */
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for (u8 dscp = 0; dscp < DSCP_MAX; dscp++) {
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int prio = ietf_dscp_to_ieee8021q_tt(dscp);
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if (prio < 0)
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return prio;
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res = yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp),
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YT921X_IPM_PRIO(prio));
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if (res)
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return res;
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}
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/* 802.1Q QoS to internal priorities */
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for (u8 pcp = 0; pcp < 8; pcp++)
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for (u8 dei = 0; dei < 2; dei++) {
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ctrl = YT921X_IPM_PRIO(pcp);
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if (dei)
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/* "Red" almost means drop, so it's not that
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* useful. Note that tc police does not support
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* Three-Color very well
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*/
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ctrl |= YT921X_IPM_COLOR_YELLOW;
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for (u8 svlan = 0; svlan < 2; svlan++) {
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u32 reg = YT921X_IPM_PCPn(svlan, dei, pcp);
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res = yt921x_reg_write(priv, reg, ctrl);
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if (res)
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return res;
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}
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}
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return 0;
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}
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static int yt921x_chip_setup(struct yt921x_priv *priv)
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{
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u32 ctrl;
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@ -2989,6 +3220,12 @@ static int yt921x_chip_setup(struct yt921x_priv *priv)
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if (res)
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return res;
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#if IS_ENABLED(CONFIG_DCB)
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res = yt921x_chip_setup_qos(priv);
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if (res)
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return res;
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#endif
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/* Clear MIB */
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ctrl = YT921X_MIB_CTRL_CLEAN | YT921X_MIB_CTRL_ALL_PORT;
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res = yt921x_reg_write(priv, YT921X_MIB_CTRL, ctrl);
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@ -3104,10 +3341,23 @@ static const struct dsa_switch_ops yt921x_dsa_switch_ops = {
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.port_mst_state_set = yt921x_dsa_port_mst_state_set,
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.vlan_msti_set = yt921x_dsa_vlan_msti_set,
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.port_stp_state_set = yt921x_dsa_port_stp_state_set,
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#if IS_ENABLED(CONFIG_DCB)
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/* dcb */
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.port_get_default_prio = yt921x_dsa_port_get_default_prio,
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.port_set_default_prio = yt921x_dsa_port_set_default_prio,
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.port_get_apptrust = yt921x_dsa_port_get_apptrust,
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.port_set_apptrust = yt921x_dsa_port_set_apptrust,
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#endif
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/* port */
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.get_tag_protocol = yt921x_dsa_get_tag_protocol,
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.phylink_get_caps = yt921x_dsa_phylink_get_caps,
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.port_setup = yt921x_dsa_port_setup,
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#if IS_ENABLED(CONFIG_DCB)
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/* dscp */
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.port_get_dscp_prio = yt921x_dsa_port_get_dscp_prio,
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.port_del_dscp_prio = yt921x_dsa_port_del_dscp_prio,
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.port_add_dscp_prio = yt921x_dsa_port_add_dscp_prio,
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#endif
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/* chip */
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.setup = yt921x_dsa_setup,
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};
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@ -3174,6 +3424,7 @@ static int yt921x_mdio_probe(struct mdio_device *mdiodev)
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ds = &priv->ds;
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ds->dev = dev;
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ds->assisted_learning_on_cpu_port = true;
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ds->dscp_prio_mapping_is_global = true;
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ds->priv = priv;
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ds->ops = &yt921x_dsa_switch_ops;
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ds->ageing_time_min = 1 * 5000;
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@ -269,6 +269,38 @@
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#define YT921X_TPID_EGRn(x) (0x100300 + 4 * (x)) /* [0, 3] */
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#define YT921X_TPID_EGR_TPID_M GENMASK(15, 0)
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#define YT921X_IPM_DSCPn(n) (0x180000 + 4 * (n)) /* Internal Priority Map */
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#define YT921X_IPM_PCPn(map, dei, pcp) (0x180100 + 4 * (16 * (map) + 8 * (dei) + (pcp)))
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#define YT921X_IPM_PRIO_M GENMASK(4, 2)
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#define YT921X_IPM_PRIO(x) FIELD_PREP(YT921X_IPM_PRIO_M, (x))
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#define YT921X_IPM_COLOR_M GENMASK(1, 0)
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#define YT921X_IPM_COLOR(x) FIELD_PREP(YT921X_IPM_COLOR_M, (x))
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#define YT921X_IPM_COLOR_GREEN YT921X_IPM_COLOR(0)
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#define YT921X_IPM_COLOR_YELLOW YT921X_IPM_COLOR(1)
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#define YT921X_IPM_COLOR_RED YT921X_IPM_COLOR(2)
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#define YT921X_PORTn_QOS(port) (0x180180 + 4 * (port))
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#define YT921X_PORT_QOS_CVLAN_PRIO_MAP_ID BIT(5)
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#define YT921X_PORT_QOS_SVLAN_PRIO_MAP_ID BIT(4)
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#define YT921X_PORT_QOS_PRIO_M GENMASK(3, 1)
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#define YT921X_PORT_QOS_PRIO(x) FIELD_PREP(YT921X_PORT_QOS_PRIO_M, (x))
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#define YT921X_PORT_QOS_PRIO_EN BIT(0)
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#define YT921X_PORTn_PRIO_ORD(port) (0x180200 + 4 * (port))
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#define YT921X_PORT_PRIO_ORD_APPm_M(m) GENMASK(3 * (m) + 2, 3 * (m))
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#define YT921X_PORT_PRIO_ORD_APPm(m, x) ((x) << (3 * (m))) /* 0: disabled, except PORT_QOS_PRIO */
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enum yt921x_app_selector {
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YT921X_APP_SEL_MAC_SA,
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YT921X_APP_SEL_MAC_DA,
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YT921X_APP_SEL_VID,
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YT921X_APP_SEL_ACL,
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YT921X_APP_SEL_DSCP,
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YT921X_APP_SEL_CVLAN_PCP,
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YT921X_APP_SEL_SVLAN_PCP,
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/* The physical port, i.e. YT921X_PORT_QOS_PRIO */
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YT921X_APP_SEL_PORT,
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YT921X_APP_SEL_NUM
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};
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#define YT921X_VLAN_IGR_FILTER 0x180280
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#define YT921X_VLAN_IGR_FILTER_PORTn_BYPASS_IGMP(port) BIT((port) + 11)
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#define YT921X_VLAN_IGR_FILTER_PORTn(port) BIT(port)
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@ -337,7 +369,7 @@
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#define YT921X_FDB_OUT0 0x1804b0
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#define YT921X_FDB_IO0_ADDR_HI4_M GENMASK(31, 0)
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#define YT921X_FDB_OUT1 0x1804b4
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#define YT921X_FDB_IO1_EGR_INT_PRI_EN BIT(31)
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#define YT921X_FDB_IO1_EGR_PRIO_EN BIT(31)
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#define YT921X_FDB_IO1_STATUS_M GENMASK(30, 28)
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#define YT921X_FDB_IO1_STATUS(x) FIELD_PREP(YT921X_FDB_IO1_STATUS_M, (x))
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#define YT921X_FDB_IO1_STATUS_INVALID YT921X_FDB_IO1_STATUS(0)
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@ -356,9 +388,9 @@
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#define YT921X_FDB_IO2_EGR_PORTS(x) FIELD_PREP(YT921X_FDB_IO2_EGR_PORTS_M, (x))
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#define YT921X_FDB_IO2_EGR_DROP BIT(17)
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#define YT921X_FDB_IO2_COPY_TO_CPU BIT(16)
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#define YT921X_FDB_IO2_IGR_INT_PRI_EN BIT(15)
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#define YT921X_FDB_IO2_INT_PRI_M GENMASK(14, 12)
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#define YT921X_FDB_IO2_INT_PRI(x) FIELD_PREP(YT921X_FDB_IO2_INT_PRI_M, (x))
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#define YT921X_FDB_IO2_IGR_PRIO_EN BIT(15)
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#define YT921X_FDB_IO2_PRIO_M GENMASK(14, 12)
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#define YT921X_FDB_IO2_PRIO(x) FIELD_PREP(YT921X_FDB_IO2_PRIO_M, (x))
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#define YT921X_FDB_IO2_NEW_VID_M GENMASK(11, 0)
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#define YT921X_FDB_IO2_NEW_VID(x) FIELD_PREP(YT921X_FDB_IO2_NEW_VID_M, (x))
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#define YT921X_FILTER_UNK_UCAST 0x180508
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@ -406,8 +438,9 @@
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#define YT921X_VLAN_CTRL_FID_M GENMASK_ULL(34, 23)
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#define YT921X_VLAN_CTRL_FID(x) FIELD_PREP(YT921X_VLAN_CTRL_FID_M, (x))
|
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#define YT921X_VLAN_CTRL_LEARN_DIS BIT_ULL(22)
|
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#define YT921X_VLAN_CTRL_INT_PRI_EN BIT_ULL(21)
|
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#define YT921X_VLAN_CTRL_INT_PRI_M GENMASK_ULL(20, 18)
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#define YT921X_VLAN_CTRL_PRIO_EN BIT_ULL(21)
|
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#define YT921X_VLAN_CTRL_PRIO_M GENMASK_ULL(20, 18)
|
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#define YT921X_VLAN_CTRL_PRIO(x) FIELD_PREP(YT921X_VLAN_CTRL_PRIO_M, (x))
|
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#define YT921X_VLAN_CTRL_PORTS_M GENMASK_ULL(17, 7)
|
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#define YT921X_VLAN_CTRL_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRL_PORTS_M, (x))
|
||||
#define YT921X_VLAN_CTRL_PORTn(port) BIT_ULL((port) + 7)
|
||||
|
|
@ -433,14 +466,14 @@
|
|||
#define YT921X_LAG_HASH_SRC_PORT BIT(0)
|
||||
|
||||
#define YT921X_PORTn_VLAN_CTRL(port) (0x230010 + 4 * (port))
|
||||
#define YT921X_PORT_VLAN_CTRL_SVLAN_PRI_EN BIT(31)
|
||||
#define YT921X_PORT_VLAN_CTRL_CVLAN_PRI_EN BIT(30)
|
||||
#define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_EN BIT(31)
|
||||
#define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_EN BIT(30)
|
||||
#define YT921X_PORT_VLAN_CTRL_SVID_M GENMASK(29, 18)
|
||||
#define YT921X_PORT_VLAN_CTRL_SVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL_SVID_M, (x))
|
||||
#define YT921X_PORT_VLAN_CTRL_CVID_M GENMASK(17, 6)
|
||||
#define YT921X_PORT_VLAN_CTRL_CVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL_CVID_M, (x))
|
||||
#define YT921X_PORT_VLAN_CTRL_SVLAN_PRI_M GENMASK(5, 3)
|
||||
#define YT921X_PORT_VLAN_CTRL_CVLAN_PRI_M GENMASK(2, 0)
|
||||
#define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_M GENMASK(5, 3)
|
||||
#define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_M GENMASK(2, 0)
|
||||
#define YT921X_PORTn_VLAN_CTRL1(port) (0x230080 + 4 * (port))
|
||||
#define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_EN BIT(8)
|
||||
#define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_PROFILE_ID_M GENMASK(7, 4)
|
||||
|
|
@ -478,6 +511,8 @@ enum yt921x_fdb_entry_status {
|
|||
#define YT921X_LAG_NUM 2
|
||||
#define YT921X_LAG_PORT_NUM 4
|
||||
|
||||
#define YT921X_PRIO_NUM 8
|
||||
|
||||
#define YT9215_MAJOR 0x9002
|
||||
#define YT9218_MAJOR 0x9001
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue