cxl: docs - add self-referencing cross-links
Add some crosslinks between pages in the CXL docs - mostly to the ACPI tables. Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-18-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
This commit is contained in:
Gregory Price
Dave Jiang
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dba600d0f2
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@ -115,7 +115,7 @@ A Multi-Headed Single-Logical Device (MHSLD) exposes a single logical
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device to multiple heads which may be connected to one or more discrete
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hosts. An example of this would be a simple memory-pool which may be
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statically configured (prior to boot) to expose portions of its memory
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to Linux via the CEDT ACPI table.
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to Linux via :doc:`CEDT <../platform/acpi/cedt>`.
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MHMLD
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~~~~~
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@ -24,7 +24,7 @@ asymmetry in properties does not happen and all paths to EPs are equal.
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There can be multiple switches under an RP. There can be multiple RPs under
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a CXL Host Bridge (HB). There can be multiple HBs under a CXL Fixed Memory
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Window Structure (CFMWS).
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Window Structure (CFMWS) in the :doc:`CEDT <../platform/acpi/cedt>`.
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An example hierarchy::
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@ -83,8 +83,9 @@ also the index for the resulting xarray.
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The next step is to take the min() of the per host bridge bandwidth and the
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bandwidth from the Generic Port (GP). The bandwidths for the GP are retrieved
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via ACPI tables SRAT/HMAT. The minimum bandwidth are aggregated under the same
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ACPI0017 device to form a new xarray.
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via ACPI tables (:doc:`SRAT <../platform/acpi/srat>` and
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:doc:`HMAT <../platform/acpi/hmat>`). The minimum bandwidth are aggregated
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under the same ACPI0017 device to form a new xarray.
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Finally, the cxl_region_update_bandwidth() is called and the aggregated
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bandwidth from all the members of the last xarray is updated for the
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@ -77,11 +77,11 @@ Root Object` Device Class is found.
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The Root contains links to:
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* `Host Bridge Ports` defined by ACPI CEDT CHBS.
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* `Host Bridge Ports` defined by CHBS in the :doc:`CEDT<../platform/acpi/cedt>`
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* `Downstream Ports` typically connected to `Host Bridge Ports`.
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* `Root Decoders` defined by ACPI CEDT CFMWS.
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* `Root Decoders` defined by CFMWS the :doc:`CEDT<../platform/acpi/cedt>`
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::
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@ -150,9 +150,8 @@ An `endpoint` is a terminal port in the fabric. This is a `logical device`,
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and may be one of many `logical devices` presented by a memory device. It
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is still considered a type of `port` in the fabric.
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An `endpoint` contains `endpoint decoders` available for use and the
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*Coherent Device Attribute Table* (CDAT) used to describe the capabilities
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of the device. ::
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An `endpoint` contains `endpoint decoders` and the device's Coherent Device
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Attribute Table (which describes the device's capabilities). ::
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# ls /sys/bus/cxl/devices/endpoint5
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CDAT decoders_committed modalias uevent
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@ -247,17 +246,18 @@ parameter.
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Root Decoder
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~~~~~~~~~~~~
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A `Root Decoder` is logical construct of the physical address and interleave
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configurations present in the ACPI CEDT CFMWS. Linux presents this information
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as a decoder present in the `CXL Root`. We consider this a `Root Decoder`,
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though technically it exists on the boundary of the CXL specification and
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platform-specific CXL root implementations.
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configurations present in the CFMWS field of the :doc:`CEDT
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<../platform/acpi/cedt>`.
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Linux presents this information as a decoder present in the `CXL Root`. We
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consider this a `Root Decoder`, though technically it exists on the boundary
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of the CXL specification and platform-specific CXL root implementations.
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Linux considers these logical decoders a type of `Routing Decoder`, and is the
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first decoder in the CXL fabric to receive a memory access from the platform's
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memory controllers.
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`Root Decoders` are created during :code:`cxl_acpi_probe`. One root decoder
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is created per CFMWS entry in the ACPI CEDT.
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is created per CFMWS entry in the :doc:`CEDT <../platform/acpi/cedt>`.
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The :code:`target_list` parameter is filled by the CFMWS target fields. Targets
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of a root decoder are `Host Bridges`, which means interleave done at the root
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@ -267,9 +267,11 @@ Only root decoders are capable of `Inter-Host-Bridge Interleave`.
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Such interleaves must be configured by the platform and described in the ACPI
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CEDT CFMWS, as the target CXL host bridge UIDs in the CFMWS must match the CXL
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host bridge UIDs in the ACPI CEDT CHBS and ACPI DSDT.
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host bridge UIDs in the CHBS field of the :doc:`CEDT
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<../platform/acpi/cedt>` and the UID field of CXL Host Bridges defined in
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the :doc:`DSDT <../platform/acpi/dsdt>`.
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Interleave settings in a rootdecoder describe how to interleave accesses among
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Interleave settings in a root decoder describe how to interleave accesses among
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the *immediate downstream targets*, not the entire interleave set.
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The memory range described in the root decoder is used to
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@ -531,10 +533,11 @@ granularity configuration.
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At Root
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~~~~~~~
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Root decoder interleave is defined by the ACPI CEDT CFMWS. The CEDT
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may actually define multiple CFMWS configurations to describe the same
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physical capacity - with the intent to allow users to decide at runtime
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whether to online memory as interleaved or non-interleaved. ::
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Root decoder interleave is defined by CFMWS field of the :doc:`CEDT
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<../platform/acpi/cedt>`. The CEDT may actually define multiple CFMWS
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configurations to describe the same physical capacity, with the intent to allow
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users to decide at runtime whether to online memory as interleaved or
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non-interleaved. ::
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Subtable Type : 01 [CXL Fixed Memory Window Structure]
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Window base address : 0000000100000000
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@ -12,8 +12,9 @@ read EFI and ACPI information throughout this process to configure logical
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representations of the devices.
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During Linux Early Boot stage (functions in the kernel that have the __init
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decorator), the system takes the resources created by EFI/BIOS (ACPI tables)
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and turns them into resources that the kernel can consume.
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decorator), the system takes the resources created by EFI/BIOS
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(:doc:`ACPI tables <../platform/acpi>`) and turns them into resources that the
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kernel can consume.
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BIOS, Build and Boot Options
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@ -70,13 +71,14 @@ significant impact performance depending on the memory capacity of the system.
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NUMA Node Reservation
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=====================
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Linux refers to the proximity domains (:code:`PXM`) defined in the SRAT to
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create NUMA nodes in :code:`acpi_numa_init`. Typically, there is a 1:1 relation
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between :code:`PXM` and NUMA node IDs.
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Linux refers to the proximity domains (:code:`PXM`) defined in the :doc:`SRAT
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<../platform/acpi/srat>` to create NUMA nodes in :code:`acpi_numa_init`.
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Typically, there is a 1:1 relation between :code:`PXM` and NUMA node IDs.
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SRAT is the only ACPI defined way of defining Proximity Domains. Linux chooses
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to, at most, map those 1:1 with NUMA nodes. CEDT adds a description of SPA
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ranges which Linux may wish to map to one or more NUMA nodes.
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The SRAT is the only ACPI defined way of defining Proximity Domains. Linux
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chooses to, at most, map those 1:1 with NUMA nodes.
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:doc:`CEDT <../platform/acpi/cedt>` adds a description of SPA ranges which
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Linux may map to one or more NUMA nodes.
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If there are CXL ranges in the CFMWS but not in SRAT, then a fake :code:`PXM`
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is created (as of v6.15). In the future, Linux may reject CFMWS not described
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@ -89,7 +91,8 @@ data for Linux to identify NUMA nodes their associated memory regions.
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The relevant code exists in: :code:`linux/drivers/acpi/numa/srat.c`.
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See the Example Platform Configurations section for more information.
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See :doc:`Example Platform Configurations <../platform/example-configs>`
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for more info.
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Memory Tiers Creation
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=====================
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@ -108,10 +111,13 @@ Tier membership can be inspected in ::
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/sys/devices/virtual/memory_tiering/memory_tierN/nodelist
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0-1
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If nodes are grouped which have clear difference in performance, check the HMAT
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and CDAT information for the CXL nodes. All nodes default to the DRAM tier,
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unless HMAT/CDAT information is reported to the memory_tier component via
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`access_coordinates`.
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If nodes are grouped which have clear difference in performance, check the
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:doc:`HMAT <../platform/acpi/hmat>` and CDAT information for the CXL nodes. All
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nodes default to the DRAM tier, unless HMAT/CDAT information is reported to the
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memory_tier component via `access_coordinates`.
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For more, see :doc:`CXL access coordinates documentation
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<../linux/access-coordinates>`.
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Contiguous Memory Allocation
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============================
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@ -22,7 +22,7 @@ At a high level, this is what occurs during this phase of configuration.
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Much of what this section is concerned with is ACPI Table production and
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static memory map configuration. More detail on these tables can be found
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under Platform Configuration -> ACPI Table Reference.
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at :doc:`ACPI Tables <acpi>`.
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.. note::
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Platform Vendors should read carefully, as this sections has recommendations
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@ -175,9 +175,9 @@ to implement driver support for your platform.
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Interleave and Configuration Flexibility
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----------------------------------------
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If providing cross-host-bridge interleave, a CFMWS entry in the CEDT must be
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presented with target host-bridges for the interleaved device sets (there may
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be multiple behind each host bridge).
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If providing cross-host-bridge interleave, a CFMWS entry in the :doc:`CEDT
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<acpi/cedt>` must be presented with target host-bridges for the interleaved
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device sets (there may be multiple behind each host bridge).
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If providing intra-host-bridge interleaving, only 1 CFMWS entry in the CEDT is
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required for that host bridge - if it covers the entire capacity of the devices
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@ -193,8 +193,8 @@ different purposes. For example, you may want to consider adding:
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A platform may choose to add all of these, or change the mode based on a BIOS
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setting. For each CFMWS entry, Linux expects descriptions of the described
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memory regions in the SRAT to determine the number of NUMA nodes it should
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reserve during early boot / init.
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memory regions in the :doc:`SRAT <acpi/srat>` to determine the number of
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NUMA nodes it should reserve during early boot / init.
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As of v6.14, Linux will create a NUMA node for each CEDT CFMWS entry, even if
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a matching SRAT entry does not exist; however, this is not guaranteed in the
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@ -18,7 +18,7 @@ Things to note:
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* This SRAT describes one node for each of the above CFMWS.
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* The HMAT describes performance for each node in the SRAT.
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CEDT ::
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:doc:`CEDT <../acpi/cedt>`::
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Subtable Type : 00 [CXL Host Bridge Structure]
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Reserved : 00
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@ -137,7 +137,7 @@ CEDT ::
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QtgId : 0001
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First Target : 00000006
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SRAT ::
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:doc:`SRAT <../acpi/srat>`::
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Subtable Type : 01 [Memory Affinity]
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Length : 28
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@ -223,7 +223,7 @@ SRAT ::
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Hot Pluggable : 1
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Non-Volatile : 0
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HMAT ::
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:doc:`HMAT <../acpi/hmat>`::
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Structure Type : 0001 [SLLBI]
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Data Type : 00 [Latency]
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@ -263,7 +263,7 @@ HMAT ::
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Entry : 0100
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Entry : 0100
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SLIT ::
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:doc:`SLIT <../acpi/slit>`::
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Signature : "SLIT" [System Locality Information Table]
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Localities : 0000000000000003
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@ -276,7 +276,7 @@ SLIT ::
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Locality 6 : FF FF FF FF FF FF 0A FF
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Locality 7 : FF FF FF FF FF FF FF 0A
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DSDT ::
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:doc:`DSDT <../acpi/dsdt>`::
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Scope (_SB)
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{
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@ -13,7 +13,7 @@ Things to note:
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* This SRAT describes one node for both host bridges.
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* The HMAT describes a single node's performance.
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CEDT ::
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:doc:`CEDT <../acpi/cedt>`::
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Subtable Type : 00 [CXL Host Bridge Structure]
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Reserved : 00
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@ -48,7 +48,7 @@ CEDT ::
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First Target : 00000007
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Second Target : 00000006
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SRAT ::
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:doc:`SRAT <../acpi/srat>`::
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Subtable Type : 01 [Memory Affinity]
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Length : 28
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@ -62,7 +62,7 @@ SRAT ::
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Hot Pluggable : 1
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Non-Volatile : 0
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HMAT ::
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:doc:`HMAT <../acpi/hmat>`::
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Structure Type : 0001 [SLLBI]
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Data Type : 00 [Latency]
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@ -80,14 +80,14 @@ HMAT ::
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Entry : 1200
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Entry : 0400
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SLIT ::
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:doc:`SLIT <../acpi/slit>`::
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Signature : "SLIT" [System Locality Information Table]
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Localities : 0000000000000003
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Locality 0 : 10 20
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Locality 1 : FF 0A
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DSDT ::
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:doc:`DSDT <../acpi/dsdt>`::
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Scope (_SB)
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{
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@ -14,7 +14,7 @@ Things to note:
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* This CEDT/SRAT describes one node for both devices.
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* There is only one proximity domain the HMAT for both devices.
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CEDT ::
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:doc:`CEDT <../acpi/cedt>`::
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Subtable Type : 00 [CXL Host Bridge Structure]
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Reserved : 00
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@ -39,7 +39,7 @@ CEDT ::
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QtgId : 0001
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First Target : 00000007
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SRAT ::
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:doc:`SRAT <../acpi/srat>`::
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Subtable Type : 01 [Memory Affinity]
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Length : 28
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@ -53,7 +53,7 @@ SRAT ::
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Hot Pluggable : 1
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Non-Volatile : 0
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HMAT ::
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:doc:`HMAT <../acpi/hmat>`::
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Structure Type : 0001 [SLLBI]
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Data Type : 00 [Latency]
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@ -69,14 +69,14 @@ HMAT ::
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Entry : 1200
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Entry : 0200
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SLIT ::
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:doc:`SLIT <../acpi/slit>`::
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Signature : "SLIT" [System Locality Information Table]
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Localities : 0000000000000003
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Locality 0 : 10 20
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Locality 1 : FF 0A
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DSDT ::
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:doc:`DSDT <../acpi/dsdt>`::
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Scope (_SB)
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{
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@ -14,7 +14,7 @@ Things to note:
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* This CEDT/SRAT describes one node per device
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* The expanders have the same performance and will be in the same memory tier.
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CEDT ::
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:doc:`CEDT <../acpi/cedt>`::
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Subtable Type : 00 [CXL Host Bridge Structure]
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Reserved : 00
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@ -62,7 +62,7 @@ CEDT ::
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QtgId : 0001
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First Target : 00000006
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SRAT ::
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:doc:`SRAT <../acpi/srat>`::
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Subtable Type : 01 [Memory Affinity]
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Length : 28
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@ -88,7 +88,7 @@ SRAT ::
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Hot Pluggable : 1
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Non-Volatile : 0
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HMAT ::
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:doc:`HMAT <../acpi/hmat>`::
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Structure Type : 0001 [SLLBI]
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Data Type : 00 [Latency]
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@ -108,7 +108,7 @@ HMAT ::
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Entry : 0200
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Entry : 0200
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SLIT ::
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:doc:`SLIT <../acpi/slit>`::
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Signature : "SLIT" [System Locality Information Table]
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Localities : 0000000000000003
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@ -116,7 +116,7 @@ SLIT ::
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Locality 1 : FF 0A FF
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Locality 2 : FF FF 0A
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DSDT ::
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:doc:`DSDT <../acpi/dsdt>`::
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Scope (_SB)
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{
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