iommu/vt-d: Fix intel iommu iotlb sync hardlockup and retry
During the qi_check_fault process after an IOMMU ITE event, requests at odd-numbered positions in the queue are set to QI_ABORT, only satisfying single-request submissions. However, qi_submit_sync now supports multiple simultaneous submissions, and can't guarantee that the wait_desc will be at an odd-numbered position. Therefore, if an item times out, IOMMU can't re-initiate the request, resulting in an infinite polling wait. This modifies the process by setting the status of all requests already fetched by IOMMU and recorded as QI_IN_USE status (including wait_desc requests) to QI_ABORT, thus enabling multiple requests to be resubmitted. Fixes:8a1d824625("iommu/vt-d: Multiple descriptors per qi_submit_sync()") Cc: stable@vger.kernel.org Signed-off-by: Guanghui Feng <guanghuifeng@linux.alibaba.com> Tested-by: Shuai Xue <xueshuai@linux.alibaba.com> Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com> Reviewed-by: Samiullah Khawaja <skhawaja@google.com> Link: https://lore.kernel.org/r/20260306101516.3885775-1-guanghuifeng@linux.alibaba.com Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Fixes:8a1d824625("iommu/vt-d: Multiple descriptors per qi_submit_sync()") Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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@ -1314,7 +1314,6 @@ static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index)
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if (fault & DMA_FSTS_ITE) {
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head = readl(iommu->reg + DMAR_IQH_REG);
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head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
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head |= 1;
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tail = readl(iommu->reg + DMAR_IQT_REG);
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tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
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@ -1331,7 +1330,7 @@ static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index)
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do {
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if (qi->desc_status[head] == QI_IN_USE)
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qi->desc_status[head] = QI_ABORT;
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head = (head - 2 + QI_LENGTH) % QI_LENGTH;
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head = (head - 1 + QI_LENGTH) % QI_LENGTH;
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} while (head != tail);
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/*
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