122 lines
3.1 KiB
C
122 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2025 AMD Corporation. All rights reserved. */
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#include <linux/types.h>
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#include <linux/aer.h>
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#include "cxl.h"
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#include "core.h"
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#include "cxlmem.h"
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void cxl_dport_map_rch_aer(struct cxl_dport *dport)
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{
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resource_size_t aer_phys;
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struct device *host;
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u16 aer_cap;
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aer_cap = cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base);
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if (aer_cap) {
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host = dport->reg_map.host;
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aer_phys = aer_cap + dport->rcrb.base;
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dport->regs.dport_aer =
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devm_cxl_iomap_block(host, aer_phys,
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sizeof(struct aer_capability_regs));
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}
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}
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void cxl_disable_rch_root_ints(struct cxl_dport *dport)
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{
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void __iomem *aer_base = dport->regs.dport_aer;
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u32 aer_cmd_mask, aer_cmd;
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if (!aer_base)
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return;
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/*
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* Disable RCH root port command interrupts.
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* CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors
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*
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* This sequence may not be necessary. CXL spec states disabling
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* the root cmd register's interrupts is required. But, PCI spec
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* shows these are disabled by default on reset.
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*/
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aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
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PCI_ERR_ROOT_CMD_NONFATAL_EN |
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PCI_ERR_ROOT_CMD_FATAL_EN);
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aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND);
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aer_cmd &= ~aer_cmd_mask;
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writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
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}
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/*
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* Copy the AER capability registers using 32 bit read accesses.
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* This is necessary because RCRB AER capability is MMIO mapped. Clear the
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* status after copying.
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*
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* @aer_base: base address of AER capability block in RCRB
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* @aer_regs: destination for copying AER capability
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*/
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static bool cxl_rch_get_aer_info(void __iomem *aer_base,
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struct aer_capability_regs *aer_regs)
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{
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int read_cnt = sizeof(struct aer_capability_regs) / sizeof(u32);
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u32 *aer_regs_buf = (u32 *)aer_regs;
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int n;
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if (!aer_base)
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return false;
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/* Use readl() to guarantee 32-bit accesses */
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for (n = 0; n < read_cnt; n++)
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aer_regs_buf[n] = readl(aer_base + n * sizeof(u32));
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writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS);
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writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS);
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return true;
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}
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/* Get AER severity. Return false if there is no error. */
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static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs,
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int *severity)
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{
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if (aer_regs->uncor_status & ~aer_regs->uncor_mask) {
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if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV)
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*severity = AER_FATAL;
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else
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*severity = AER_NONFATAL;
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return true;
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}
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if (aer_regs->cor_status & ~aer_regs->cor_mask) {
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*severity = AER_CORRECTABLE;
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return true;
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}
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return false;
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}
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void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)
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{
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struct pci_dev *pdev = to_pci_dev(cxlds->dev);
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struct aer_capability_regs aer_regs;
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struct cxl_dport *dport;
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int severity;
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struct cxl_port *port __free(put_cxl_port) =
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cxl_pci_find_port(pdev, &dport);
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if (!port)
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return;
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if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs))
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return;
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if (!cxl_rch_get_aer_severity(&aer_regs, &severity))
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return;
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pci_print_aer(pdev, severity, &aer_regs);
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if (severity == AER_CORRECTABLE)
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cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras);
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else
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cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras);
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}
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