39 lines
1.1 KiB
C
39 lines
1.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
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#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* R9A09G087 CPG Core Clocks */
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#define R9A09G087_CLK_CA55C0 0
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#define R9A09G087_CLK_CA55C1 1
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#define R9A09G087_CLK_CA55C2 2
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#define R9A09G087_CLK_CA55C3 3
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#define R9A09G087_CLK_CA55S 4
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#define R9A09G087_CLK_CR52_CPU0 5
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#define R9A09G087_CLK_CR52_CPU1 6
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#define R9A09G087_CLK_CKIO 7
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#define R9A09G087_CLK_PCLKAH 8
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#define R9A09G087_CLK_PCLKAM 9
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#define R9A09G087_CLK_PCLKAL 10
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#define R9A09G087_CLK_PCLKGPTL 11
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#define R9A09G087_CLK_PCLKH 12
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#define R9A09G087_CLK_PCLKM 13
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#define R9A09G087_CLK_PCLKL 14
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#define R9A09G087_SDHI_CLKHS 15
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#define R9A09G087_USB_CLK 16
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#define R9A09G087_ETCLKA 17
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#define R9A09G087_ETCLKB 18
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#define R9A09G087_ETCLKC 19
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#define R9A09G087_ETCLKD 20
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#define R9A09G087_ETCLKE 21
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#define R9A09G087_XSPI_CLK0 22
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#define R9A09G087_XSPI_CLK1 23
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#define R9A09G087_PCLKCAN 24
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#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
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