343 lines
12 KiB
Rust
343 lines
12 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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//! PCI memory-mapped I/O infrastructure.
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use super::Device;
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use crate::{
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bindings,
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device,
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devres::Devres,
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io::{
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io_define_read,
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io_define_write,
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Io,
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IoCapable,
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IoKnownSize,
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Mmio,
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MmioRaw, //
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},
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prelude::*,
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sync::aref::ARef, //
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};
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use core::{
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marker::PhantomData,
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ops::Deref, //
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};
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/// Represents the size of a PCI configuration space.
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///
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/// PCI devices can have either a *normal* (legacy) configuration space of 256 bytes,
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/// or an *extended* configuration space of 4096 bytes as defined in the PCI Express
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/// specification.
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#[repr(usize)]
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#[derive(Eq, PartialEq)]
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pub enum ConfigSpaceSize {
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/// 256-byte legacy PCI configuration space.
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Normal = 256,
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/// 4096-byte PCIe extended configuration space.
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Extended = 4096,
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}
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impl ConfigSpaceSize {
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/// Get the raw value of this enum.
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#[inline(always)]
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pub const fn into_raw(self) -> usize {
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// CAST: PCI configuration space size is at most 4096 bytes, so the value always fits
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// within `usize` without truncation or sign change.
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self as usize
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}
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}
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/// Marker type for normal (256-byte) PCI configuration space.
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pub struct Normal;
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/// Marker type for extended (4096-byte) PCIe configuration space.
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pub struct Extended;
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/// Trait for PCI configuration space size markers.
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///
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/// This trait is implemented by [`Normal`] and [`Extended`] to provide
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/// compile-time knowledge of the configuration space size.
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pub trait ConfigSpaceKind {
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/// The size of this configuration space in bytes.
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const SIZE: usize;
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}
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impl ConfigSpaceKind for Normal {
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const SIZE: usize = 256;
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}
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impl ConfigSpaceKind for Extended {
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const SIZE: usize = 4096;
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}
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/// The PCI configuration space of a device.
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///
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/// Provides typed read and write accessors for configuration registers
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/// using the standard `pci_read_config_*` and `pci_write_config_*` helpers.
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///
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/// The generic parameter `S` indicates the maximum size of the configuration space.
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/// Use [`Normal`] for 256-byte legacy configuration space or [`Extended`] for
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/// 4096-byte PCIe extended configuration space (default).
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pub struct ConfigSpace<'a, S: ConfigSpaceKind = Extended> {
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pub(crate) pdev: &'a Device<device::Bound>,
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_marker: PhantomData<S>,
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}
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/// Internal helper macros used to invoke C PCI configuration space read functions.
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///
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/// This macro is intended to be used by higher-level PCI configuration space access macros
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/// (io_define_read) and provides a unified expansion for infallible vs. fallible read semantics. It
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/// emits a direct call into the corresponding C helper and performs the required cast to the Rust
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/// return type.
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///
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/// # Parameters
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///
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/// * `$c_fn` – The C function performing the PCI configuration space write.
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/// * `$self` – The I/O backend object.
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/// * `$ty` – The type of the value to read.
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/// * `$addr` – The PCI configuration space offset to read.
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///
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/// This macro does not perform any validation; all invariants must be upheld by the higher-level
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/// abstraction invoking it.
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macro_rules! call_config_read {
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(infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) => {{
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let mut val: $ty = 0;
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// SAFETY: By the type invariant `$self.pdev` is a valid address.
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// CAST: The offset is cast to `i32` because the C functions expect a 32-bit signed offset
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// parameter. PCI configuration space size is at most 4096 bytes, so the value always fits
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// within `i32` without truncation or sign change.
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// Return value from C function is ignored in infallible accessors.
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let _ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as i32, &mut val) };
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val
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}};
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}
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/// Internal helper macros used to invoke C PCI configuration space write functions.
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///
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/// This macro is intended to be used by higher-level PCI configuration space access macros
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/// (io_define_write) and provides a unified expansion for infallible vs. fallible read semantics.
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/// It emits a direct call into the corresponding C helper and performs the required cast to the
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/// Rust return type.
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///
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/// # Parameters
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///
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/// * `$c_fn` – The C function performing the PCI configuration space write.
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/// * `$self` – The I/O backend object.
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/// * `$ty` – The type of the written value.
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/// * `$addr` – The configuration space offset to write.
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/// * `$value` – The value to write.
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///
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/// This macro does not perform any validation; all invariants must be upheld by the higher-level
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/// abstraction invoking it.
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macro_rules! call_config_write {
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(infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) => {
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// SAFETY: By the type invariant `$self.pdev` is a valid address.
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// CAST: The offset is cast to `i32` because the C functions expect a 32-bit signed offset
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// parameter. PCI configuration space size is at most 4096 bytes, so the value always fits
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// within `i32` without truncation or sign change.
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// Return value from C function is ignored in infallible accessors.
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let _ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as i32, $value) };
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};
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}
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// PCI configuration space supports 8, 16, and 32-bit accesses.
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impl<'a, S: ConfigSpaceKind> IoCapable<u8> for ConfigSpace<'a, S> {}
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impl<'a, S: ConfigSpaceKind> IoCapable<u16> for ConfigSpace<'a, S> {}
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impl<'a, S: ConfigSpaceKind> IoCapable<u32> for ConfigSpace<'a, S> {}
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impl<'a, S: ConfigSpaceKind> Io for ConfigSpace<'a, S> {
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/// Returns the base address of the I/O region. It is always 0 for configuration space.
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#[inline]
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fn addr(&self) -> usize {
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0
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}
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/// Returns the maximum size of the configuration space.
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#[inline]
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fn maxsize(&self) -> usize {
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self.pdev.cfg_size().into_raw()
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}
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// PCI configuration space does not support fallible operations.
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// The default implementations from the Io trait are not used.
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io_define_read!(infallible, read8, call_config_read(pci_read_config_byte) -> u8);
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io_define_read!(infallible, read16, call_config_read(pci_read_config_word) -> u16);
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io_define_read!(infallible, read32, call_config_read(pci_read_config_dword) -> u32);
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io_define_write!(infallible, write8, call_config_write(pci_write_config_byte) <- u8);
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io_define_write!(infallible, write16, call_config_write(pci_write_config_word) <- u16);
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io_define_write!(infallible, write32, call_config_write(pci_write_config_dword) <- u32);
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}
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impl<'a, S: ConfigSpaceKind> IoKnownSize for ConfigSpace<'a, S> {
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const MIN_SIZE: usize = S::SIZE;
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}
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/// A PCI BAR to perform I/O-Operations on.
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///
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/// I/O backend assumes that the device is little-endian and will automatically
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/// convert from little-endian to CPU endianness.
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///
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/// # Invariants
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///
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/// `Bar` always holds an `IoRaw` instance that holds a valid pointer to the start of the I/O
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/// memory mapped PCI BAR and its size.
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pub struct Bar<const SIZE: usize = 0> {
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pdev: ARef<Device>,
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io: MmioRaw<SIZE>,
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num: i32,
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}
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impl<const SIZE: usize> Bar<SIZE> {
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pub(super) fn new(pdev: &Device, num: u32, name: &CStr) -> Result<Self> {
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let len = pdev.resource_len(num)?;
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if len == 0 {
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return Err(ENOMEM);
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}
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// Convert to `i32`, since that's what all the C bindings use.
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let num = i32::try_from(num)?;
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// SAFETY:
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// `pdev` is valid by the invariants of `Device`.
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// `num` is checked for validity by a previous call to `Device::resource_len`.
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// `name` is always valid.
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let ret = unsafe { bindings::pci_request_region(pdev.as_raw(), num, name.as_char_ptr()) };
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if ret != 0 {
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return Err(EBUSY);
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}
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// SAFETY:
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// `pdev` is valid by the invariants of `Device`.
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// `num` is checked for validity by a previous call to `Device::resource_len`.
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// `name` is always valid.
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let ioptr: usize = unsafe { bindings::pci_iomap(pdev.as_raw(), num, 0) } as usize;
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if ioptr == 0 {
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// SAFETY:
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// `pdev` is valid by the invariants of `Device`.
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// `num` is checked for validity by a previous call to `Device::resource_len`.
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unsafe { bindings::pci_release_region(pdev.as_raw(), num) };
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return Err(ENOMEM);
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}
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let io = match MmioRaw::new(ioptr, len as usize) {
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Ok(io) => io,
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Err(err) => {
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// SAFETY:
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// `pdev` is valid by the invariants of `Device`.
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// `ioptr` is guaranteed to be the start of a valid I/O mapped memory region.
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// `num` is checked for validity by a previous call to `Device::resource_len`.
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unsafe { Self::do_release(pdev, ioptr, num) };
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return Err(err);
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}
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};
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Ok(Bar {
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pdev: pdev.into(),
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io,
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num,
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})
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}
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/// # Safety
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///
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/// `ioptr` must be a valid pointer to the memory mapped PCI BAR number `num`.
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unsafe fn do_release(pdev: &Device, ioptr: usize, num: i32) {
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// SAFETY:
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// `pdev` is valid by the invariants of `Device`.
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// `ioptr` is valid by the safety requirements.
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// `num` is valid by the safety requirements.
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unsafe {
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bindings::pci_iounmap(pdev.as_raw(), ioptr as *mut c_void);
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bindings::pci_release_region(pdev.as_raw(), num);
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}
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}
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fn release(&self) {
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// SAFETY: The safety requirements are guaranteed by the type invariant of `self.pdev`.
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unsafe { Self::do_release(&self.pdev, self.io.addr(), self.num) };
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}
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}
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impl Bar {
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#[inline]
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pub(super) fn index_is_valid(index: u32) -> bool {
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// A `struct pci_dev` owns an array of resources with at most `PCI_NUM_RESOURCES` entries.
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index < bindings::PCI_NUM_RESOURCES
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}
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}
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impl<const SIZE: usize> Drop for Bar<SIZE> {
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fn drop(&mut self) {
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self.release();
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}
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}
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impl<const SIZE: usize> Deref for Bar<SIZE> {
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type Target = Mmio<SIZE>;
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fn deref(&self) -> &Self::Target {
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// SAFETY: By the type invariant of `Self`, the MMIO range in `self.io` is properly mapped.
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unsafe { Mmio::from_raw(&self.io) }
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}
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}
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impl Device<device::Bound> {
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/// Maps an entire PCI BAR after performing a region-request on it. I/O operation bound checks
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/// can be performed on compile time for offsets (plus the requested type size) < SIZE.
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pub fn iomap_region_sized<'a, const SIZE: usize>(
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&'a self,
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bar: u32,
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name: &'a CStr,
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) -> impl PinInit<Devres<Bar<SIZE>>, Error> + 'a {
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Devres::new(self.as_ref(), Bar::<SIZE>::new(self, bar, name))
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}
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/// Maps an entire PCI BAR after performing a region-request on it.
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pub fn iomap_region<'a>(
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&'a self,
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bar: u32,
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name: &'a CStr,
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) -> impl PinInit<Devres<Bar>, Error> + 'a {
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self.iomap_region_sized::<0>(bar, name)
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}
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/// Returns the size of configuration space.
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pub fn cfg_size(&self) -> ConfigSpaceSize {
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// SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`.
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let size = unsafe { (*self.as_raw()).cfg_size };
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match size {
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256 => ConfigSpaceSize::Normal,
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4096 => ConfigSpaceSize::Extended,
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_ => {
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// PANIC: The PCI subsystem only ever reports the configuration space size as either
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// `ConfigSpaceSize::Normal` or `ConfigSpaceSize::Extended`.
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unreachable!();
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}
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}
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}
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/// Return an initialized normal (256-byte) config space object.
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pub fn config_space<'a>(&'a self) -> ConfigSpace<'a, Normal> {
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ConfigSpace {
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pdev: self,
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_marker: PhantomData,
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}
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}
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/// Return an initialized extended (4096-byte) config space object.
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pub fn config_space_extended<'a>(&'a self) -> Result<ConfigSpace<'a, Extended>> {
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if self.cfg_size() != ConfigSpaceSize::Extended {
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return Err(EINVAL);
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}
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Ok(ConfigSpace {
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pdev: self,
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_marker: PhantomData,
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})
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}
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}
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