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Jesse Taube 04a2aef59c RISC-V: fix vector insn load/store width mask RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits. Replace GENMASK(3, 0) with GENMASK(2, 0). Fixes: `cd05483724` ("riscv: Allocate user's vector context in the first-use trap") Signed-off-by: Jesse Taube <jesse@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20240606182800.415831-1-jesse@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	2024-06-25 08:47:10 -07:00
..
asm	RISC-V: fix vector insn load/store width mask	2024-06-25 08:47:10 -07:00
uapi/asm	RISC-V Patches for the 6.10 Merge Window, Part 1	2024-05-22 09:56:00 -07:00

RISC-V: fix vector insn load/store width mask

RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
Replace GENMASK(3, 0) with GENMASK(2, 0).

Fixes: cd05483724 ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: Jesse Taube <jesse@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240606182800.415831-1-jesse@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

2024-06-25 08:47:10 -07:00

asm RISC-V: fix vector insn load/store width mask 2024-06-25 08:47:10 -07:00

uapi/asm RISC-V Patches for the 6.10 Merge Window, Part 1 2024-05-22 09:56:00 -07:00